International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 12, December 2013

FPGA Implementation of Wallace Tree Multiplier using CSLA / CLA

Shruti Dixit, Praveen Kumar Pandey

This paper discusses two different architectures of Wallace Tree Multiplier and analyses which one is better in respect of area and power consumption in order to fortify the multiplier design. In one of the architecture the final addition is performed using Carry look-ahead adder whereas in the other architecture the final addition is performed using Carry select adder. The proposed design in this paper is implemented on FPGA Spartan 3e and simulation tools used are Xilinx and Modelsim.

Keywords: Wallace tree multiplier, CSLA, CSA, Xilinx, FPGA

Edition: Volume 2 Issue 12, December 2013

Pages: 314 - 318


How to Cite this Article?

Shruti Dixit, Praveen Kumar Pandey, "FPGA Implementation of Wallace Tree Multiplier using CSLA / CLA ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=02013644, Volume 2 Issue 12, December 2013, 314 - 318

26 PDF Views | 26 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Wallace tree multiplier'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2387 - 2390

Design of Wallace Tree Multiplier using Adiabatic Logic

Bhushan V. Mude, Prof. R. N. Mandavgane, Prof. A. P. Bagde

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 12, December 2013

Pages: 314 - 318

FPGA Implementation of Wallace Tree Multiplier using CSLA / CLA

Shruti Dixit, Praveen Kumar Pandey

Share this article

Similar Articles with Keyword 'CSLA'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2737 - 2741

A Hierarchical Design of High Performance Carry Select Adder Using Reversible Logic

Amol D. Rewatkar, R. N. Mandavgane, S. R. Vaidya

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 8 Issue 11, November 2019

Pages: 964 - 967

Low Power and Area Efficient Carry Select Adder Using D-Flip Flop

S. Muminthaj, S. Kayalvizhi, K. Sangeetha

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2997 - 3000

Area Efficient architecture for 64 bit CSLA using Sum and Carry Generation Unit

Mahadev Bobade, M. N. Kakatkar

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 2, February 2016

Pages: 1444 - 1447

An Efficient Architecture of Carry Select Adder Using Logic Formulation

Kaveri.N, Senthil Kumar.P

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 2242 - 2245

Design and Implementation of 64-Bit Multiplier Using CLAA and CSLA

Shaik Meerabi, Krishna Prasad Satamraju

Share this article

Similar Articles with Keyword 'CSA'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 2836 - 2840

A Survey Paper on FPGA-Based Broken Bar Detection of Induction Motor Using Motor Current Signature Analysis

Manoj B. Pavale, K. J. Amrutkar

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 2029 - 2034

An Enhanced Residue Modular Multiplier for Cryptography

Vundela Sarada

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1069 - 1074

Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

Mariya Stephen, Vrinda

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 10, October 2014

Pages: 2344 - 2348

Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm by using A VLSI Architecture

A. Sathya, S. Fathimabee, S. Divya

Share this article

Similar Articles with Keyword 'Xilinx'

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2374 - 2378

Circuit under Test Verification with MSIC Test Pattern Generator

Parvathy Chandra, Vishnu V. S.

Share this article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1332 - 1335

Low Power Self-Timed TCAM Based on Overlapped Search Mechanism with IP Filter Implementation

Jerrin Paul M, Hazel Elsa John

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 642 - 645

Low Power and Area Optimized VHDL Implementation of AES

Suja Chackochan, K. Mathan

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 648 - 650

Design and Performance Analysis of Serial Peripheral Interface

Gaurav Anand, Shelly Gahlawat

Share this article

Similar Articles with Keyword 'FPGA'

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this article

Review Papers, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1378 - 1381

Design and Analysis of Double Precision Floating Point Division Operator Based on CORDIC Algorithm

Chetan Dudhagave, Hari Krishna Moorthy

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2476 - 2479

Software Defined Radio Signal Detector Implementation using FPGA

Rohan Fernandes, Shubhangi Mahamuni

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2430 - 2432

Development of Low Cost Smart Antenna System and its FPGA Implementation

Harshveer Singh Grewal, Paramveer Singh Gill

Share this article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1350 - 1355

Implementation, Simulation and Synthesis of RSA Cryptosystem

Rafeek Alas, Dr. Kiran Bailey

Share this article

Top