Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 10, October 2013

Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques

K. Mallikarjuna, V. LakshmiVasudha

Most of the VLSI applications, such as DSP, image & video processing, and microprocessors, extensively use logic gates and arithmetic circuits. 1-bit full adder cell is the extensively use in arithmetic circuits. Gate diffusion input (GDI) a new technique of low-power digital combinational circuit designis described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. In this paper an area and power efficient 9T adder design has been presented by hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 PMOS. A PTL based 5T XOR-XNOR module has been proposed to improve area at 65nm technology and compared with the previous XOR-XNOR design. The proposed Hybrid full adder design is based on this area efficient 5T XOR-XNOR module design. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the proposed full adder. Also the simulation of layout and parametric analysis has been done for the proposed full adder design. The performance of the proposed technique is evaluated and compared by implementing it in 8-bit CLA adder, 4-bit RCA adder, 4-bit CSkA adder, 4-bit CSelA adder, 4-bit CSaA adder, ,. Several logic circuits have been implemented in various design styles. Their properties are discussed; simulation results are reported, and presented.

Keywords: Gate Diffusion Input, Pass transistor logic, CMOS, VLSI

Edition: Volume 2 Issue 10, October 2013

Pages: 210 - 216

Share this Article

How to Cite this Article?

K. Mallikarjuna, V. LakshmiVasudha, "Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=02013317, Volume 2 Issue 10, October 2013, 210 - 216

80 PDF Views | 72 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Gate Diffusion Input'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 1188 - 1190

Design of GDI Based Low Power and High-Speed CMOS Full Adder Circuits

M. Krishna Kumar, Prof. D. Shanthi Chelliah

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1205 - 1210

A Novel Low power and Area Efficient Carry-Lookahead Adder Using MOD-GDI Technique

Pinninti Kishore, P. V. Sridevi, K. Babulu, K.S Pradeep Chandra

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 7, July 2017

Pages: 1831 - 1837

Low Power-Delay Design of 4-Bit ALU Using GDI Technique and Its Comparison

Sukesh B Pednekar, Sheela Kore

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 902 - 907

Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits

Shreedevi, Taranath H. B

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 10, October 2013

Pages: 210 - 216

Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques

K. Mallikarjuna, V. LakshmiVasudha

Share this Article

Similar Articles with Keyword 'Pass transistor logic'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 4, April 2017

Pages: 1915 - 1919

Low-Power and High?Performance Design Techniques for CMOS 4-bit ALU by using CPL, DPL, DVL

Jagruty Naik

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 4, April 2013

Pages: 183 - 187

A Novel Pass Transistor Logic Based Pulse Triggered Flip-flop with Conditional Enhancement

Shakthipriya.R, Kirthika.N

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 10, October 2013

Pages: 210 - 216

Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques

K. Mallikarjuna, V. LakshmiVasudha

Share this Article

Similar Articles with Keyword 'CMOS'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots' Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2270 - 2274

Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology

Daya Nand Gupta, S. R. P. Sinha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 9, September 2014

Pages: 943 - 949

Design and Analysis of CMOS Multipliers at 180nm and 350nm

Jagmeet Singh, Hardeep Singh

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 257 - 260

Low Phase Noise Ring Oscillator Using Current Steering Technique

G. Gopal, Sri M. Madhusudhan Reddy

Share this Article

Similar Articles with Keyword 'VLSI'

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 264 - 267

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booth's Multiplier

Sarwagya Chaudhary

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2561 - 2564

Statistical Simulation for BIST Architecture using Cognitive Principles

Shradha Khemka

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 2270 - 2274

Design and Simulation of NOT and NAND Gate Using Hybrid SET-MOS Technology

Daya Nand Gupta, S. R. P. Sinha

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2313 - 2315

Review of Fully Reused VLSI Architecture of Channel Encoding Using SOLS Technique for DSRC Applications

Supriya S. Garade, P. R. Badadapure

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 2257 - 2262

VLSI Implementation of an Optical OFDM Transmitter Using 180nm Technology

Arunlal.K.S, Saravanan.V

Share this Article
Top