Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 7, July 2013

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier

Sarwagya Chaudhary

An arithmetic logic unit acts as the basic building block or cell of a central processing unit of a computer. It is a digital circuit, comprised of the basic electronic components, which is used to perform various arithmetic, logic and integral operations..The purpose of this work is to propose the design of an 8-bit ALU which supports 4-bit multiplication. The functionalities of the ALU in this study consist of addition, subtraction, increment, decrement, AND, OR, NOT, XOR, NOR, twos complement generation, multiplication. The adder in the ALU is implemented using a Carry Look Ahead adder joined by a ripple carry approach. The design of the multiplier is achieved using the Booths Algorithm. The proposed ALU can be designed by using Verilog or VHDL and can also be designed on Cadence Virtuoso Platform.

Keywords: Arithmetic Logic Unit, Booth Multiplier, Carry Look-Ahead Adder, VLSI

Edition: Volume 2 Issue 7, July 2013

Pages: 264 - 267

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How to Cite this Article?

Sarwagya Chaudhary, "Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booths Multiplier", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=02013170, Volume 2 Issue 7, July 2013, 264 - 267

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